Before starting, it should be noted that the Ryzen 5000 are not direct heirs to AMD Ryzen 4000 which are monolithic SoCs, but rather Ryzen 3000 as Ryzen 5000 are also MCM systems based on chiplets.
In this system, on the one hand IOD where is the North Bridge systems located , was baptized as AMD’s Scalable Data Structure or SDF and Southbridge called I / O Hub by Raisenov and Radeonov. The IOD listed hasn’t changed compared to the Ryzen 3000, except for the fact that it supports faster memory, since it is through the IOD that the cores have access to the system’s RAM.
However, we cannot say that they took the Ryzen 3000 IO Die as it is and transplanted it as it is, but that they improved it through their experience building the Ryzen 4000 for computers with lower power consumption than a desktop PC.
So where were really important changes happened in CCD or Core Complex Die , a small chip that stores the various cores and their cache hierarchy, where the most important changes took place.
New Core Complex Die Architecture Zen 3
CCD in Zen 2 was drawn up of two CCX with 4 cores each, with its own L3 cache is used in each CCX … which causes a series of latency issues where multiple cores in one CCD but in different CCX had to communicate, since if a core was to communicate with another that was in another CCX, then it had to go through the IOD despite the fact that it was on the same CCD.
The change AMD made to the Zen 3 architecture is very simple, they made 8 cores sharing L3 cache instead of 4. kernels simultaneously … Thus, we have abandoned two 2-core CCXs per CCD. up to 1 8-core CCX on CCD … This provides a performance advantage in applications designed to run on 8 or fewer cores.
But where is A MD made improvements at the level of each core is in Loading / storing units , And also in front end or control unit improvements that were key to achieving an average performance of 19% over its predecessor, Zen 2.
The key is the control unit
When we talk about Front-End we mean CPU control unit and ALU means Back-end. V training cycle fetch-decode-execute, the first two stages – the operation of the control unit , and the second part is the work of ALU or execution units.
Everything modern x86 processors not follow instructions as specified by ISA but instead decode instructions in internal ISA RISC this is where the instructions are actually executed in the execution units. This internal ISA can change even between members of the same architecture and is key when increasing the IPC of processors.
That is why AMD remade control unit and implemented new, much more efficient internal ISA this allows instructions to be executed in fewer clock cycles per instruction (CPI), resulting in an increase in the average number of instructions per clock cycle. …