NVMe PCIe 5.0 standard: features and differences from 4.0

One of the principles of performance is that the system is as slow as the slowest part of it will allow. This is why, to achieve performance, it seeks not only to increase the speed of components such as processors and RAM, but also storage units. This is achieved through the adoption of various PCIe standards for NVMe drives.

What is a Flash Controller?

Controladora NVMe PCIe Flash

A flash controller is the hardware that sits between NVMe memory or any other type of NAND flash and the CPU or GPU / GPU that wants to access it. Its job is to translate virtual addresses into physical addresses that provide direct access to the NVMe memory blocks that make up the SSD storage unit.

Today, when a processor or GPU accesses any memory space, it does so using shared addressing, which combines all the memories it has access to in a hierarchy. The various MMUs, integrated in both the CPU and GPU, are responsible for communicating with different types of memory in the system, RAM, VRAM, as well as non-volatile RAM or NVRAM, which is NVMe memory in solid state drives.

But virtual addressing is different from physical addressing, and therefore a translation process is needed, which is performed by a flash controller. To do this, it uses memory from which it stores address translation tables, source data in the form of virtual addressing, and destination data in the form of physical addressing. Such memory can be found on an NVMe solid state drive, it can be system RAM in the case of a DRAM-free design, or it can be embedded as on-board memory in the flash controller itself.

NVMe PCIe 5.0 Flash Drivers Overview

Marvel Bravera SC5 NVMe PCIe 5.0

One of the first flash controllers to support PCI Express 5.0 is Marvell Bravera SC5 … This allows data to be transferred at a bandwidth of 14 GB / s on a 4-line PCI Express 5.0 bus, which means doubling the bandwidth in relation to the same number of lines with PCI Express 4.0, but does not mean bus saturation. in both cases, as they can go as high as 16 GB / s and 7 GB / s respectively.

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Be aware that a flash controller works the same way as interfaces that link RAM or VRAM to CPUs and GPUs. They are responsible for handling read and write requests made by the processor. And since today we already have several cores in the CPU, it is very important that the flash controller has a large number of access channels. V Marvell Bravera SC5 has 16 channels in total, so you can connect up to 16 single-channel or 8 dual-channel NAND Flash chips to it.

Channels are the number of NVMe memory chips that the flash controller can talk to at the same time. Low NVMe SSDs usually have 2 or 4 channels, high performance 8 channels and we have special cases like PlayStation 5 SSD with 12 channels. The fact that the Marvell Bravera SC5 has 16 channels not only allows it to have more storage capacity, but also shows that it is a controller aimed at the server market and not for home PCs.

High bandwidth requires high processing power

Puente Binario

Moving data from one memory to another is one of the biggest nightmares hardware architects have faced in the history of computing. Bulk movement requires the CPU or GPU to have a good time performing the appropriate operations for it. This is why hardware systems have been created since time immemorial that transfer data from one memory to another without the participation of the main processor and do it in much less time.

The fact that an NVMe SSD can be accessed through a PCI Express port, such as a GPU, does not mean that it can be accessed directly without impacting performance. In next-gen consoles such as the PlayStation 5 and both Xbox In Series X, the inclusion of NVMe SSDs has led to the integration of specialized modules responsible for transferring, compressing and decompressing data from the SSD to memory, which they strive to free up the CPU and GPU. systems from such a load.

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On a PC, only NVIDIA and AMD graphics cards with DirectX 12 Ultimate support have such blocks. This leads to the need to harness computing power to control the movement of data. If the CPU or GPU is not fast enough to execute this control, a daisy-chain effect is created that causes all subsequent requests to be delayed, thereby delaying the shared data sent in a fraction of the time.

What are the benefits of NVMe PCIe 5.0 SSDs besides faster speed?


Since they represent a linear evolution over those using the PCIe 4.0 interface, we can say that this is quite small, but the launch of internal NVMe SSDs with PCIe 5.0 will coincide with the rollout of the NVMe 2.0 standard, which will provide a series of benefits that go beyond increasing the speed of the bus. Thus, both factors will be combined to improve this type of storage in the near future.

Although, if we have to highlight the improvement in PCIe 5.0, especially this this is Compute Express Link support or CXL. This is a feature. which will initially only be on servers and will simplify access to equipment. Cause? It provides direct access to NVMe SSD without going through the Southbridge IOMMU, reducing access latency and allowing the implementation of a flash controller in the CPU, GPU or APU itself, or even using the PCIe CXL interface for direct access to DIMMs combining NVMe and DDR5 chips together …

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